A Spacetime device reconfigures on the fly at multi-GHz rates, executing each portion of a design in an automatically defined sequence of steps. Although manufactured using a standard CMOS process, Spacetime uses this ultra-rapid reconfiguration to make Time a third dimension, resulting in a 3D device with multiple layers or folds in which computation and signal transmission can occur. Each fold performs a portion of the desired function and stores the result in place. When some or all of a fold is reconfigured, it uses the locally stored data to perform the next portion of the function. By rapidly reconfiguring to execute different portions of each function, a 3D Spacetime device can implement a complex design using only a small fraction of the resources that would be required by an inherently 2D FPGA. A designer can realize all of the benefits of 3D within a familiar methodology using the Spacetime compiler that automatically maps standard RTL into Spacetime.

Spacetime devices will provide significantly higher logic, memory and signal processing capabilities than FPGAs, and their much higher density makes them suitable for volume production.

2.5x LOGIC DENSITY Unlike FPGAs, Spacetime devices are capable of dynamically changing configurations at multi-GHz frequency. As a result, logic, memory and routing resources are all re-used multiple times per user cycle, enabling much higher density and shorter interconnect than FPGAs.

2.0x MEMORY DENSITY FPGAs use large dual-port memory cells for their embedded memory blocks to support the multi-port functionality required in most communications and data processing applications. Spacetime memories provide greater multi-port flexibility while using twice denser single-port memory cells.

2.9x MEMORY PORTS FPGA memories have 2 ports, whereas Spacetime memories have 8 or 16 ports. Many communications and data-processing applications can take advantage of such multi-ported memories which enable functions such as broadcast, muxing, de-muxing multiple channels of data, and 2-read/1-write register files.

3.7x DSP PERFORMANCE The logic fabric on FPGAs run much more slowly than the hard multipliers, which limits practical DSP throughput to that of the slow fabric, rather than that of the fast multiplier. In contrast, with Spacetime, logic fabric, memories, and DSP blocks can all run at 1.6 GHz, which eliminates this bottleneck. The resulting high-speed pipelines in Spacetime are setting new standards for signal processing performance.