COMPANY FAST FACTS:
Founded by EDA pioneer, Steve Teig 130+ employees
145+ patents granted
3250 Olcott St.
Santa Clara, CA 95054
Phone: (408) 986-9140
Fax: (408) 986-9146
ANALYST, PRESS INQUIRES:
Sabrina Joseph, Managing Partner
560 S. Winchester Blvd., Suite 500
San Jose, CA 95128
This is made possible by a Spacetime hardware capable of dynamically reconfiguring at multi-GHz rates and by the Stylus compiler that transparently manages this ultra-rapid reconfiguration of logic, memory, and interconnect resources throughout the chip. As a result, Spacetime creates a third dimension of Space by using Time.
A Spacetime device reconfigures on the fly at multi-GHz rates executing each portion of a design in an automatically defined sequence of steps. Manufactured using a standard CMOS process, Spacetime uses this ultra-rapid reconfiguration to make Time a third dimension. This results in a 3D device with multiple layers or “folds” in which computation and signal transmission can occur. Each fold performs a portion of the desired function and stores the result in place. When some or all of a fold is reconfigured, it uses the locally stored data to perform the next portion of the function. By rapidly reconfiguring to execute different portions of each function, a 3D Spacetime device can implement a complex design using only a small fraction of the resources that would be required by an FPGA, with its inherently 2D architecture.
This ultra-rapid reconfiguration enables Spacetime to deliver a breakthrough in programmable logic price/performance and capabilities. As a result, Spacetime products combine the flexibility and rapid time-to-market of an FPGA with ASIC capacity, at price points suitable for volume production.