Technology

The Spacetime Clock

In Spacetime the user clock which is input into the Tabula device is divided into sub-cycles which form the folds. The first generation of Tabula device core clocks at up to 1.6 GHz. A user clock of, for example, 200 MHz is divided into eight folds. Higher user clock speeds can be used with fewer folds. For example, a 400 MHz user clock can be divided into four folds. The device core operates using these folds, enabling up to eight operations per user-clock cycle. Figure 2 shows an eight-fold Spacetime clock.

Dividing the user clock into folds enables multiple operations to be performed in the device core for each user clock cycle.



Figure 3 provides an example of why the shorter interconnect paths enabled by the effective use of local resources results both in greater density and higher performance. In FPGA architectures, data is routed to resources in various physical locations. Paths vary in length and therefore access time. In Tabula devices, the data is kept within a much smaller physical area with resources in reach within one fold.



In eight folds, the Tabula device handles the same data using substantially fewer on-chip resources.

In addition to increased resource density, Spacetime architecture results in a substantial performance increase compared to FPGA architectures. All resources can be modified and reused including memory port configurations and address spaces. LUTs can be changed on each fold resulting in the same physical logic being multifunctional. Instead of routing data to a resource elsewhere on-chip, the data can be processed locally. If routing elsewhere is required, shortest-path routing can be configured in one fold. These optimizations are determined at user-design compile time by the Spacetime compiler, which generates a configuration bit-stream loaded into the device configuration memory at power-on.

The high-frequency Subcycle clock combined with the inherently shorter paths in the Spacetime architecture mean reduced processing time thus resulting in high throughput with a small die size.

As shown in Figure 4, Spacetime also requires less resources for data interconnect and routing because narrower data paths are used compared to those found in FPGAs. A narrow 8-bit wide path in (8 folds) delivers 64 bits that would require a wide 64-bit data path in an FPGA.