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To meet the increasing complexity of today's electronic systems, the integration of programmable logic devices and development tools must be completely seamless, enable increasingly better price/performance, and provide designers with a familiar design environment supporting industry standard design languages, constraints specifications and scripting. In support of Tabula's Spacetime™ architecture and ABAX™ family of 3PLD devices, Tabula introduces the Stylus™ software cloud computing design platform. Designers can now harness computing power through the web from cloud resources to take full advantage of Tabula's breakthrough Spacetime 3D architecture, accelerating end-product time-to-market at lower costs. The industry's first integrated synthesis and place-and-route (SP&R) package
supporting 3PLD devices, Stylus manages the underlying reconfiguration transparently, automatically mapping standard RTL into Spacetime. In addition, it combines leading-edge synthesis technology with 3D timing-driven place-and-route within a flow and methodology which are familiar to FPGA and ASIC designers, thus requiring little or no learning curve.
Stylus Cloud Computing Software Brochure >
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COMPILES DESIGNS IN HDL TO ABAX READY BITSTREAMS
| INPUTS |
OUTPUTS |
- Design entry in VHDL and Verilog
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- RTL and gate-level simulation netlists
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- Timing constraints specified in standard SDC format
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- Integrated Tcl support for scripting with GUI/command line interoperability
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- Implementation reports: resource utilization and results from each step of the flow
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- General directives such as pin placement
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- Bitstreams for programming ABAX parts
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FULLY INTEGRATED SP&R SYSTEM
With an integrated SP&R system supported by a browser-like GUI; Stylus offers an intuitive familiar design environment for ASIC and FPGA designers. At the heart of Stylus is Spacetime-optimized synthesis coupled with timing-driven 3D place-and-route. Stylus enables designers to realize all of the benefits of 3D by automatically and transparently mapping standard RTL directly into Spacetime. Stylus' integrated GUI links logical, physical, and schematic project views giving developers the ability to analyze all aspects of a design together. Several productivity-enhancing features have been implemented such as advanced floor-planning, static timing, and power analysis. In addition, Stylus provides on-chip debug capabilities by supporting the integration of debug logic and direct probing of select nodes in a user circuit. Stylus offers seamless integration of soft IP cores from Tabula's leading IP partners, and supports design libraries for industry standard simulators.
ABAX PRODUCT FAMILY
Tabula's ABAX family of 3PLD Devices represents a new category of general-purpose chips. Leveraging Tabula's breakthrough Spacetime architecture,
ABAX delivers programmability with unprecedented capabilities at volume price points.
| FEATURES |
A1EC02 |
A1EC03 |
A1EC04 |
| MegaLUT |
0.22 |
0.30 |
0.39 |
| MegaBYTEs RAM |
5.5 |
5.5 |
5.5 |
| RegFile Blocks |
960 |
960 |
960 |
| LRAM (Large RAM) Blocks |
480 |
480 |
480 |
| MRAM (Medium RAM) Blocks |
240 |
240 |
240 |
| Multiplier/Accumulator Blocks |
- |
- |
- |
| Parallel I/Os |
920 |
920 |
920 |
| SerDes (55 Mb/s - 6.5 Gb/s) |
48 |
48 |
48 |
| PLLs |
44 |
44 |
44 |
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SPACETIME FABRIC
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- Logic: 0.22 MegaLUT to 0.63 MegaLUT operating at up to 1.6 GHz
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- Memory: 5.5 MBYTES of high-performance 1.6 GHz RAM
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- DSP blocks: up to 1280 1.6 GHz, configurable, 18x18 multiplier
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- High-performance clock network supporting 1.6 GHz operations
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