COMPANY FAST FACTS:
Founded by EDA pioneer, Steve Teig 145+ patents granted
3250 Olcott St.
Santa Clara, CA 95054
Phone: (408) 986-9140
Fax: (408) 986-9146
ANALYST, PRESS INQUIRES:
Sabrina Joseph, Managing Partner
560 S. Winchester Blvd., Suite 500
San Jose, CA 95128
Tabula is implementing a next-generation family of 3PLD products manufactured by Intel using its advanced 22nm manufacturing process featuring 3-D Tri-Gate transistors and co-optimized packaging technology. This is made possible by a manufacturing access agreement between Tabula Inc., and Intel Custom Foundry, a division of the Technology and Manufacturing Group of Intel Corporation. The 3PLD family will be based on Tabula's next-generation 3D Spacetime architecture and will deliver high-performance, cost-effective solutions for network infrastructure systems requiring high-bandwidth data flows such as Switches, Routers, Packet Inspection appliances, and other high-performance systems. The combination of process and architecture will allow Tabula to produce high-performance programmable circuits that consume significantly less chip area than circuits implemented with traditional FPGA fabrics.
What is Spacetime?
Spacetime is an innovative programmable logic architecture developed by Tabula that uses time as a third dimension to create 3D programmable devices (3PLD) with smaller die size, shorter interconnect, and higher capabilities than traditional FPGAs. The concept leverages rapid reconfiguration of the entire chip to re-use all the chip's resources multiple times in a single system clock cycle. It does this by dividing the system clock cycle time into multiple subcycles and then changes the logic configuration every subcycle to make it appear as if all the logic for the entire clock cycle is present. Stylus, the software tool developed by Tabula, hides the complexity of the Spacetime approach and preserves a traditional design methodology to allow designers to quickly port their designs. At the heart of Stylus is Spacetime-optimized synthesis coupled with timing-driven 3D place-and-route. Stylus enables designers to realize all of the benefits of 3D by automatically and transparently mapping standard RTL directly into Spacetime. Stylus accepts standard VHDL/Verilog/System Verilog inputs as well as SDC constraints.
A Spacetime programmable device reconfigures on the fly at multi-Gigahertz rates, executing each portion of a design in an automatically defined sequence of steps. The tools divide each clock cycle into multiple subcycles referred to as "folds" (layers) in which computation and signal transmission can occur (see the figure). Each fold performs a portion of the desired function that would execute in the full system clock cycle. When some or all of a fold is reconfigured, it uses the locally stored data to perform the next portion of the function. By rapidly reconfiguring to execute different portions of the layered function, a Spacetime programmable logic fabric can implement a complex design using only a small fraction of the resources that would be required by a traditional FPGA fabric.
Reducing interconnect by building 3D Programmable Logic Devices
In traditional FPGA fabrics, interconnect is the biggest challenge since the complex circuits designers want to implement demand minimal internal delays and higher and higher operating frequencies. As FPGAs have become larger, and with the advent of 100 Gigabit Ethernet requirements, the traditional FPGAs are reaching their performance limits and bottlenecks are appearing when data moves between memory and I/O ports, and in DSP and logic functions. Eliminating these limitations, Tabula's novel Spacetime programmable fabric delivers a balanced architecture with dramatically shorter interconnects than traditional FPGAs and the ability to clock the entire fabric – logic, DSP, memory, and interconnect -- at the same frequency. To do that, the Spacetime architecture uses time as a third dimension to reduce the number of components needed to implement a function and can thus deliver smaller, higher performance, more cost-effective chips that are well suited for a wide range of applications, spanning telecommunications, enterprise networking, and wireless infrastructure markets.
About the Intel 22nm Process featuring 3D Tri-Gate transistors
The Intel Tri-Gate transistor structure implemented in a 22-nm process both shrinks the size of the transistors thanks to the smaller features, but also thanks to the extra gate elements on the transistors, greatly enhances the transistor performance. The 3-D Tri-Gate transistor uses three conducting gates wrapped around a vertical fin structure (the silicon channel in a 3-D structure), providing fully-depleted operation and thus enabling an exceptional combination of performance and energy efficiency.
Thus, current flow is controlled on three sides of the channel (top, left and right) rather than just from the top, as in conventional planar transistors (see the figure). The net result is much better control of the transistor, maximizing current flow (for best performance) when it is on, and minimizing it (reducing leakage) when it is off. Additionally, the small features, coupled with the better gate control, allow the transistors to switch very fast, thus permitting logic fabrics to operate at multi-GHz clock speeds.
For more about the Tri-Gate 22nm technology go to: