Design & Reuse IP-SOC 2011 Conference
Marc Miller, Sr. Director of Marketing
"Rise and Fall of New Fabless Startups -> New Model for IP/ASSP Collaboration"
December 7, 2011
Grenoble, France
http://www.design-reuse.com/ipsoc2011

IP SoC Village Presentation
Marc Miller, Sr. Director of Marketing
"ASAP™ Program – A New Platform for ASSPs"
Monday, June 6 at 3:00pm
Embedded Theatre
Exhibit Hall F – Booth #1825
San Diego Convention Center, CA
http://www.dac.com/


Interop May 8-12, Las Vegas, Mandalay Bay
http://www.interop.com/lasvegas/
Booth #1675



Thursday, Nov 18, 2010 Time: 11am EDT - 6pm EDT - 6 month archive
EETimes Virtual Conference System-on-chip 2.0
Keynote:
"A new computing paradigm for the 21st century" by Steve Teig, Founder, President and CTO of Tabula

Abstract:
Today's System-on-Chip (SoC) devices involve multiple processors and multiple hardware accelerators in closely-coupled or networked topologies. In addition to tiered memory structures and multi-layer bus structures, these systems - which may be executing hundreds of millions to tens of billions of instructions per second - feature extremely complex software components, and this software content is currently increasing almost exponentially.

The "von Neumann architecture" for computers, which was popularized by the Hungarian American mathematician John von Neumann, has now dominated computing for more than 65 years. It is a masterpiece of simplicity: readily implemented in hardware, easily understood by software developers, and amenable to compilation from a wide variety of programming languages. Unfortunately, it achieves its simplicity from the fundamental, non-physical assumption that reading from a memory location takes negligible, constant time independent of the size of the memory.

Decades of innovation in computer architecture and compiler design for uniprocessors has masked some of the von Neumann computer's intrinsic latency. The power requirements for this disguise have become prohibitive, though, which has ended the long, exponential rise in uniprocessor clock frequency. Multi-core processors, the semiconductor industry's response, have the virtue that they can clearly be built, but no one knows how to program them! Further, they make the same negligible-latency assumptions as uniprocessors, but disguising that latency is now quadratically more difficult.

In his keynote presentation, Steve Teig will show that highly useful yet non-physical oversimplifications such as the von Neumann architecture have numerous historical precedents from which we can learn. These examples suggest that a more physically aware, non-von Neumann machine could offer significantly higher-performance and far more power-efficient computation. Steve will also present some thoughts on what such a machine might look like - hint: it is not an array of microprocessors! - and how one might program it. It is only by simultaneously approaching architecture, hardware, and software - seeing them as aspects of a cohesive whole as von Neumann did - that we can maximize our chances of going beyond von Neumann computing.


Wednesday Dec 1, 2010, Gent, Belgium
Symposium "A new era for high-level synthesis"
"Spacetime: a programmable fabric beyond the FPGA" by Steve Teig, Founder, President and CTO of Tabula

Abstract:
Programmable fabrics, such as FPGAs, have existed since at least 1984, but commercial FPGA architectures have stagnated over the last decade, leaving today's FPGAs with the same 20-50x price/performance disadvantage vs. ASICs that they had 10 years ago. Spacetime is a new approach to constructing a programmable fabric, based on novel, ultra-high-performance, sub-ns-reconfigurable hardware coupled with an easily grasped metaphor that completely hides the underlying, on-the-fly reconfiguration, thus facilitating the automated mapping of computations to the fabric. While the idea of reconfiguration is not new, dating back to Turing or even earlier, the representation of the temporal aspects of computing in a spatial way, as Special Relativity does for physics, is new, and Minkowski's space-time geometry concisely encapsulates key requirements for the correctness and performance of computations mapped to MIMD fabrics, such as FPGAs, multi-core microprocessors, and Tabula's 3PLDs. As such, our embodiment of these ideas in Spacetime offers not only a 5x price/performance advantage vs. FPGA but also vital aspects of the compiler technology that will be required for multi-core and other multi-computing hardware implementations.


Tuesday, June 15, 2010 Time: 12:00 PM — 2:00 PM
DAC, Design Automation Conference
Anaheim, CA Location: 303AB
"Beyond von Neumann Computing" by Steve Teig, Founder, President and CTO of Tabula

Event Press Release>

Register today to meet with the Tabula Sales and Marketing team at DAC.
Booth #294 at the TSMC Open Innovation Forum, Analog Bits

April 13, 2010
TSMC 2010 U.S. Tech Symposium
San Jose, California
Tabula to demo SerDes at the TSMC symposium in our partner Analog Bits booth #14 and #15


March 29-31, 2010
SNUG Synopsys Users Group
Santa Clara, CA, Santa Clara Convention Center
Using StarRC OpenAccess Interface for Accurate and Productive Custom IC Design Paper Presentation
by Mahesh Kondajji Sr. Staff Engineer CAD at Tabula