Tabula.com | Applications | Tabula ABAX Solution

Communications equipment vendors developing solutions for next generation networks require a flexible platform with high performance capability. In addition, they need to get to market quickly and keep costs down. With Tabula's ABAXTM product family, equipment suppliers now have access to a tehnologically advanced platform that delivers superior compute power at competitive price points.

Tabula ABAX devices have higher logic density, higher memory density, higher memory port count, and higher DSP performance than 40 nm FPGAs. They also offer significant advantages over alternative ASIC and ASSP solutions.

A key advantage resulting from Spacetime architecture is that a large device can be obtained from a physically smaller one. This translates directly into more capabilities at a lower cost. To fully appreciate this benefit, consider the cost of the largest FPGA. These so-called "reticle busters ¹" yield so poorly that the resulting devices may cost several thousands of dollars a piece. With Spacetime architecture, a device with superior capabilities than the reticle buster would physically be implemented on a much smaller die. Since the smaller die results in more die/wafer, and those die yield much better than the largest die, the cost of the smaller die would be significantly lower. Hence a Tabula device that has superior capabilites than the largest FPGA has a dramatically lower cost that is suitable for volume production.

The ABAX product family implements an innovative architecture called Spacetime that enables the devices to achieve superior density and capability for logic, memory, and signal processing:

THE SPACETIME ARCHITECTURE TRIPLE PLAY

Logic
Memory
DSP

Tabula Spacetime architecture uses time as a third dimension to bring the density and performance of 3-D to programmable logic, while maintaining a standard design flow. The result is a new class of programmable devices called 3PLDs that combine ASIC capability with FPGA ease of use at volume price points.

This is made possible by a Spacetime hardware capable of dynamically reconfiguring at multi-GHz rates and by the Spacetime compiler that transparently manages this ultra-rapid reconfiguration of logic, memory, and interconnect resources throughout the chip: As a result,Spacetime emulates a third dimension of Space by using Time.

The benefits of the Spacetime architecture include higher logic density and a smaller footprint with significantly shorter interconnects when compared with FPGA's 2-D architecture.

One of the subtleties of the Spacetime architecture is that not only is logic denser, but memory and signal processing elements also make more efficient use of each square millimeter of silicon. You might ask how is this possible when Tabula devices use standard CMOS process. Here's the trick for memories. Spacetime memories are denser because its workhorse memories use single-port bit cells. Single-port bit cells are twice as dense as dual-port bit cells. FPGAs use dual-port bit cells because dual-port memories are often required in communications and other applications. How does Spacetime architecture solve this problem? The high-speed Spacetime clock allows 8 accesses to each memory cell per cycle. This effectively turns the single-port bit cell into an 8-port cell. Paradoxically, a bit cell that has 2x the density has 4x the ports.

Any design can be easily ported and take advantage of the denser memory. Additionally, the door is opened for innovative design techniques that use the 8-ported memories for:

- Broadcast
- Muxing, de-muxing multiple channels of data
- 2-read/1-write register files
- Other new structures

ABAX devices contain more than double the user memory capacity relative to high-end FPGAs, making them suitable and cost effective for applications where use of external memory can be avoided with further SoC integration. In many cases entire banks of QDR memories can be removed from the board and on-chip memory can be used instead

Of course wireless baseband processing is signal-processing intensive. FPGAs add hundreds of standard cell multiplier/accumulators to accelerate these functions. The fundamental conundrum for FPGA companies has been the frequency mismatch between the standard-cell multipliers and programmable logic. The logic just could not keep up.

The Spacetime architecture solves this puzzle. The internal Spacetime clock runs at multi-GHz frequencies matching the speed of the hard multipliers. As a result, memories, logic, and DSP elements can join in a high-speed pipeline that sets new standards for signal-processing performance. This high-speed pipeline is automatically set-up by the Spacetime compiler.

1 Industry parlance used to describe the largest chip that can be manufactured.
2 ASSP products can enable rapid time-to-market only if a specific product has already been developed and can simply be purchased off the shelf. However, for Next-Gen networks, such products are often not available since ASSP vendors face product risks if they lock their features too early while industry standards undergo revisions.