Tabula Announces Availability of Stylus Compiler Version 2.8.2
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Tabula Announces Availability of Stylus Compiler Version 2.8.1
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MoSys Announces Tabula Support of GigaChip Interface
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Intel Developers Forum
September 9-11, 2014
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Linley Group Carrier Conference
System design for wired and wireless infrastructure
June 10-11, 2014
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Ethernet Technology Summit
40/100/400 GbE | data centers | SDN | Internet-of-things
April 29- May 1, 2014
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Tabula's Four Core Technology Components

3PLD Devices

The ABAX2P1 3PLD chip is a 12‐fold Spacetime device that delivers unique RAM and logic fabric capabilities alongside tailored, hard IP blocks.

Stylus Compiler

The compiler integrates cutting‐edge technologies: sequential timing, router-aware placement, & automatic co‐optimization of performance.

3D Architecture

The Spacetime 3D architecture employs time, as a third dimension, rapidly reprogramming every resource on the chip.


Intel's 3D Tri‐Gate transistors, the most advanced in the world, provide unmatched speed at low operating voltage for reduced power.



4x100G switch reference design kit
12x10G‐to‐100G bridge reference design kit
2nd‐generation Ternary Search Engine (TSE2) reference design kit