Stylus provides a synthesis, placement, and routing flow familiar to FPGA designers and uses industry-standard RTL and design constraints. It automatically exploits the unique advantages of Tabula's Spacetime 3D architecture, unleashing the ABAX2 3PLDs' unmatched capabilities and achieving unparalleled performance with surprising ease.
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Carrier Conference 2013
June 12-13, 2013
Hyatt Regency Hotel, Santa Clara, CA
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Carrier Conference 2013
June 12-13, 2013
Hyatt Regency Hotel, Santa Clara, CA
Tabula's Four Core Technology Components
3PLD Devices
The ABAX2P1 3PLD chip is a 12‐fold Spacetime device that delivers unique RAM and logic fabric capabilities alongside tailored, hard IP blocks.
Stylus Compiler
The compiler integrates cutting‐edge technologies: sequential timing, router-aware placement, & automatic co‐optimization of performance.
3D Architecture
The Spacetime 3D architecture employs time, as a third dimension, rapidly reprogramming every resource on the chip.
Intel PROCESS
Intel's 3D Tri‐Gate transistors, the most advanced in the world, provide unmatched speed at low operating voltage for reduced power.
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4x100G switch reference design kit |
12x10G‐to‐100G bridge reference design kit |
2nd‐generation Ternary Search Engine (TSE2) reference design kit |
